Title :
A fully working 0.14 /spl mu/m DRAM technology with polymetal (W/WN/sub x//poly-Si) gate
Author :
Jong-Wan Jung ; Seok-Woo Lee ; Yong-Gyu Sung ; Byung-Hak Lee ; Jun-Ho Choi ; Bong-Jae Lee ; Rae-Hak Park ; Sang-Beom Han
Author_Institution :
Hyundai Electron. Ind. Co. Ltd., Cheongju, South Korea
Abstract :
A fully working 0.14 /spl mu/m -256 Mbit DRAM with polymetal gate (W/WN/sub x//poly-Si) for word line was implemented for the first time. For full integration of polymetal word line, we adopted several key technologies related to W process which include etching, cleaning, and selective oxidation process. The sheet resistance of a 700 /spl Aring//700 /spl Aring/ WN/sub x//poly-Si polymetal was uniform (<3 /spl Omega//sq. at 0.14 /spl mu/m) through full integration, and reliability characteristics were also compatible to conventional WSi/sub x//poly-Si gate. By applying polymetal word line and PPP (pre poly plug) cell scheme, we successfully implemented 0.14 /spl mu/m -256 DRAM.
Keywords :
DRAM chips; elemental semiconductors; etching; field effect memory circuits; integrated circuit reliability; integrated circuit technology; oxidation; silicon; surface cleaning; tungsten; tungsten compounds; 0.14 micron; 256 Mbit; 700 angstrom; DRAM technology; W-WN-Si; cleaning; etching; polymetal gate; pre poly plug cell; reliability characteristics; selective oxidation process; sheet resistance; word line; Cleaning; Electric breakdown; Impurities; Oxidation; Plugs; Random access memory; Space technology; Temperature; Very large scale integration; Wet etching;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904331
