Title :
The analysis of spot defect induced faults in MOS circuits
Author :
Di, Chennian ; De Gyvez, Jose Pine
Author_Institution :
Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
Abstract :
A strategy for modeling spot defect induced faults by their corresponding Boolean functions is developed. The presented strategy is based on the principle of local conduction path analysis. This way of modeling is much more general in the sense that all kinds of faults are unified by one concept, the Boolean function. In this way testing related applications can be done efficiently and can maintain a high quality
Keywords :
Boolean functions; MOS integrated circuits; combinatorial circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; Boolean functions; MOS circuits; NMOS combinational circuits; local conduction path analysis; spot defect induced faults; testing; Boolean functions; Bridge circuits; Circuit analysis; Circuit faults; Circuit testing; Circuit topology; Combinational circuits; Logic testing; MOS devices; Variable structure systems;
Conference_Titel :
Circuits and Systems, 1991. Conference Proceedings, China., 1991 International Conference on
Conference_Location :
Shenzhen
DOI :
10.1109/CICCAS.1991.184394
