DocumentCode
2885807
Title
Low thermal budget elevated source/drain technology utilizing novel solid phase epitaxy and selective vapor phase etching
Author
Miyano, K. ; Mizushima, I. ; Hokazono, A. ; Ohuchi, K. ; Tsunashima, Y.
Author_Institution
Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
fYear
2000
fDate
10-13 Dec. 2000
Firstpage
433
Lastpage
436
Abstract
A new low thermal-budget process for elevated source/drain (S/D) structure was developed utilizing novel solid phase epitaxy (SPE) followed by vapor phase selective etching. Short channel characteristics were drastically improved compared to those attainable with the conventional selective epitaxial growth process. Bridging problems, which had been regarded as unavoidable, were also cleared. This newly developed process is a potential solution for the elevated S/D structure in 0.1 /spl mu/m devices and beyond.
Keywords
MOSFET; etching; oxidation; solid phase epitaxial growth; TEM; bridging problems; elevated source/drain technology; interfacial oxygen; leakage current; low thermal-budget process; oxide mediated SPE; shallow junction formation; short channel characteristics; solid phase epitaxy; vapor phase selective etching; Cleaning; Crystallization; Epitaxial growth; Epitaxial layers; Etching; Manufacturing processes; Semiconductor device manufacture; Solids; Systems engineering and theory; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-6438-4
Type
conf
DOI
10.1109/IEDM.2000.904349
Filename
904349
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