Title :
Low temperature (800/spl deg/C) recessed junction selective silicon-germanium source/drain technology for sub-70 nm CMOS
Author :
Gannavaram, S. ; Pesovic, N. ; Ozturk, C.
Author_Institution :
North Carolina State Univ., Raleigh, NC, USA
Abstract :
We present a novel, low-temperature source/drain junction and contact formation technology applicable to sub-70 nm CMOS. In this process, in-situ boron doped SiGe is selectively deposited at 500/spl deg/C in the source/drain windows recessed to the desired junction depth. The technology meets the NTRS roadmap requirements for (i) junction depth/sheet resistance (<100 /spl Omega//sq. for 30 nm junctions), (ii) ultra-low resistivity contacts (1.5/spl times/10/sup -8/ /spl Omega/-cm/sup 2/), (iii) excellent reverse leakage characteristics (less than 1% of the I/sub OFF/ budget), (iv) perfect box-shaped lateral abruptness and (v) thermal integration compatibility with high-k gate dielectrics using the conventional (gate-last) CMOS process flow.
Keywords :
CMOS integrated circuits; Ge-Si alloys; chemical vapour deposition; contact resistance; dielectric thin films; integrated circuit metallisation; leakage currents; rapid thermal processing; semiconductor materials; sputter etching; 30 to 70 nm; 500 to 800 degC; CMOS; NTRS roadmap requirements; SiGe; contact formation technology; gate-last process flow; high-k gate dielectrics; junction depth; junction depth/sheet resistance; perfect box-shaped lateral abruptness; recessed junction selective source/drain technology; reverse leakage characteristics; source/drain windows; thermal integration compatibility; ultra-low resistivity contacts; Annealing; Boron; CMOS process; CMOS technology; Capacitive sensors; Conductivity; Etching; Germanium silicon alloys; Silicon germanium; Temperature;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904350
