Title :
Highly reliable poly-SiGe/amorphous-Si gate CMOS
Author :
Uejima, K. ; Yamamoto, T. ; Mogami, T.
Author_Institution :
Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan
Abstract :
We have developed highly reliable poly-SiGe-gated CMOS devices using a poly-SiGe/a-Si (3 nm) gate structure for sub-0.1 /spl mu/m CMOS devices. It was found that by adding a thin amorphous-Si (a-Si) layer, Q/sub BD/(50%) is improved compared with the conventional poly-SiGe and even with pure poly-Si N/PMOS devices. Furthermore, low gate depletion was obtained for the poly-SiGe/a-Si gate. The polarity dependence of the Q/sub BD/ improvement suggests that the a-Si layer reduces a "weak reliability layer" of SiO/sub 2/ near the SiGe/SiO/sub 2/ interface. Appreciably higher performance of poly-SiGe/a-Si gate N/PMOSFETs was demonstrated compared with conventional poly-Si gate N/PMOSFETs.
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; amorphous semiconductors; elemental semiconductors; integrated circuit measurement; integrated circuit reliability; semiconductor materials; silicon; silicon compounds; 1.5 to 2 nm; CMOS; NMOSFETs; PMOSFETs; Si-SiGe-Si-SiO/sub 2/; gate depletion; polarity dependence; weak reliability layer; Annealing; Capacitive sensors; Capacitors; Degradation; Design for quality; Fluctuations; Germanium silicon alloys; MOS devices; National electric code; Silicon germanium;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904352
