DocumentCode :
2885860
Title :
Modeling power-supply disturbances in digital circuit
Author :
Cortes, Meritxell ; McCluskey, E. ; Wagner, Karl ; Lu, Dan
Author_Institution :
Stanford University, Stanford, CA, USA
Volume :
XXIX
fYear :
1986
fDate :
19-21 Feb. 1986
Firstpage :
164
Lastpage :
165
Abstract :
A model that represents errors caused by power supply disturbances as delay faults will be discussed. Experiments reveal that the error susceptibility increases at high clock rates and that metastable states may result.
Keywords :
CMOS logic circuits; Circuit testing; Detectors; Digital circuits; Frequency; Logic circuits; Power supplies; Propagation delay; Semiconductor device modeling; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
Type :
conf
DOI :
10.1109/ISSCC.1986.1157008
Filename :
1157008
Link To Document :
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