Title :
Fast RNS DSP algorithms implemented with binary arithmetic
Author :
Di Claudio, E.D. ; Orlandi, G. ; Piazza, F.
Author_Institution :
Telettra SpA, Chieti Scalo, Italy
Abstract :
Fast RNS (residue number system) algorithms which use only binary arithmetic are developed. Scaled residues, called pseudoresidues, are introduced by exploiting the cycle properties of each RNS channel and solving a Diophantine equation. Using the pseudoresidues instead of the original residue set to perform the desired computations, an RNS processor can be built with standard binary devices of small wordlength. The effectiveness of the procedure is shown by developing the pseudoresidue implementations of a modular multiplier for odd moduli RNS and of a FIR (finite impulse response) filter. The resulting structures exhibit complete reprogrammability for both moduli and coefficients, a very low number of fast machine cycles, and a square time-area product reduction
Keywords :
computerised signal processing; digital arithmetic; digital filters; multiplying circuits; DSP algorithms; Diophantine equation; FIR filter; RNS channel; RNS processor; binary arithmetic; binary devices; coefficients; cycle properties; fast RNS algorithms; finite impulse response; machine cycles; modular multiplier; odd moduli RNS; pseudoresidues; residue number system; scaled residues; square time-area product reduction; wordlength; Arithmetic; Bismuth; Digital signal processing; Equations; Finite impulse response filter; Hardware; Logic design; Random access memory; Read only memory; Read-write memory;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on
Conference_Location :
Albuquerque, NM
DOI :
10.1109/ICASSP.1990.115701