Title :
Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology
Author :
Hirano, Y. ; Matsumoto, T. ; Maeda, Shigenobu ; Iwamatsu, T. ; Kunikiyo, T. ; Nii, K. ; Yamamoto, K. ; Yamaguchi, Y. ; Ipposhi, T. ; Maegawa, S. ; Inuishi, M.
Author_Institution :
ULSI Dev. Centre, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 /spl mu/m era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-relate speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk structure. Moreover, it is shown that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI´s. It is concluded that SOI technology with HTI structure is one of the solutions against the scaling limitations.
Keywords :
CMOS memory circuits; SRAM chips; isolation technology; silicon-on-insulator; 0.1 micron; 4 Mbit; SOI CMOS; SRAM; Si; body-tied hybrid trench isolation structure; full trench isolation; gate thinning; one-chip integration; scaling; soft error rate; CMOS technology; Circuit simulation; Degradation; Error analysis; Isolation technology; Large scale integration; MOSFET circuits; Pulse measurements; Random access memory; Silicon;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904357
