Title :
A CML compatible GaAs gate array
Author :
Hirayama, Hiroshi ; Furutsuka, T. ; Tanaka, Yuichi ; Kaga, M. ; Kanamori, Mitsuru ; Takahashi, Koichi ; Kohzu, H. ; Higashisaka, A.
Author_Institution :
NEC LSI Development Div., Microelectronics Research Laboratories, Kawasaki, Japan
Abstract :
This paper will describe a CML compatible GaAs 3K array using buffered FET logic. Propagation delays of 59ps and 186ps per gate were achieved for load conditions of 65μm and 2mm line lengths, respectively. 32b shift register operation at 1.2 GHz clock rates was verified.
Keywords :
Capacitance; Diodes; FETs; Gallium arsenide; Large scale integration; Logic arrays; Logic circuits; Propagation delay; Semiconductor device measurement; Shift registers;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1157018
