VLSI implementation of the hippocampus on nonlinear system model

Author

Chen, Oscal T C ; Berger, Theodore ; Sheu, Bing J.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

4

fYear

1994

fDate

27 Jun-2 Jul 1994

Firstpage

2009

Abstract

The nonlinear model of the functional properties of the hippocampal formation has been developed. The architecture of the proposed hardware implementation has a topology highly similar to the anatomical structure of the hippocampus, and the dynamical properties of its components are based on experimental characterization of individual hippocampal neurons. The design scheme of a analog cellular neural network has been extensively applied. By using a 1-μm CMOS technology, the 5×5 neuron array with some testing modules has been designed for fabrication. According to the SPICE-3 circuit simulator, the response time of each neuron with memorizing 4 time units is around 0.5 μsec

Keywords

CMOS analogue integrated circuits; SPICE; analogue processing circuits; cellular neural nets; mixed analogue-digital integrated circuits; neural chips; nonlinear systems; physiological models; 1 mum; 1-μm CMOS technology; 5×5 neuron array; SPICE-3 circuit simulator; VLSI implementation; analog cellular neural network; functional properties; hippocampus; mixed analog/digital processor; nonlinear system model; response time; Anatomical structure; CMOS technology; Cellular neural networks; Circuit testing; Hardware; Hippocampus; Network topology; Neurons; Nonlinear systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-1901-X

Type

conf

DOI

10.1109/ICNN.1994.374521

Filename

374521