Author :
Young, K.K. ; Wu, S.Y. ; Wu, C.C. ; Wang, C.H. ; Lin, C.T. ; Cheng, J.Y. ; Chiang, M. ; Chen, S.H. ; Lo, T.C. ; Chen, Y.S. ; Chen, J.H. ; Chen, L.J. ; Hou, S.Y. ; Law, J.J. ; Chang, T.E. ; Hou, C.S. ; Shih, J. ; Jeng, S.M. ; Hsieh, H.C. ; Ku, Y. ; Yen, T.
Abstract :
A leading-edge 0.13 /spl mu/m CMOS technology using 193 nm lithography and Cu/low-k interconnect is described in this paper. High performance 80 nm core devices use 17 /spl Aring/ nitrided oxide for 1.0-1.2 V operation. These devices deliver unloaded 8.5 ps gate delay @1.2 V. This technology also supports general ASIC applications with 20 /spl Aring/ oxide for 1.2-1.5 V operation and low-standby power applications with 26 /spl Aring/ for 1.5 V operation, respectively. Dual gate oxides of 50 or 65 /spl Aring/ are also supported for 2.5 V or 3.3 V I/O circuits respectively. Cu with low-k dielectric is used for the 8-layer metal interconnect system with tight pitch. The aggressive design rules and border-less contacts/vias support a high density 1P3M 2.43 /spl mu/m/sup 2/ 6T-SRAM cell without local interconnect. A suite of embedded SRAM cells (6T, 8T) with competitive density and performance optimized for different applications are also supported with memory compilers and large block macros.
Keywords :
CMOS memory circuits; SRAM chips; application specific integrated circuits; copper; integrated circuit interconnections; low-power electronics; ultraviolet lithography; 0.13 micron; 1.0 to 1.2 V; 1.2 to 1.5 V; 193 nm; 2.5 V; 3.3 V; ASIC; CMOS technology; DUV lithography; SRAM cell; copper interconnect; dual gate oxide; gate delay; input/output circuit; low-k dielectric; low-power design; nitrided oxide; Annealing; Application specific integrated circuits; CMOS technology; Delay; Implants; Integrated circuit interconnections; Lithography; MOSFETs; Random access memory; Semiconductor device manufacture;
