A 2.05 um/sup 2/ full CMOS ultra-low power SRAM cell with 0.15 nm generation single gate CMOS technology

Author

Jang, J.H. ; Kim, H.S. ; Baek, H.C. ; Na, J.J. ; Lee, K.H. ; Seo, D.S. ; Kim, K.J. ; Kim, K.T. ; Shin, Y.S. ; Hwang, C.G.

Author_Institution

SRAM-1 Team, Samsung Electron. Co. Ltd., Yongin City, South Korea

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

579

Lastpage

582

Abstract

We have developed a 2.05 um/sup 2/ full-CMOS ultra-low power SRAM Cell, which is probably the world-smallest, using 0.15 um generation single gate CMOS technology. The technology includes i) 0.15 um direct contact (to active region and gate poly) implemented by phase shift mask (PSM) and the shrinkage of contact by photo-resist (PR) reflow, ii) W-damascened local interconnection with 0.30 um pitch, iii) careful optimization of 0.17 um gate length buried channel (BC) pMOS to minimize the leakage current, while excludes self-aligned contact, Co-salicide, and rapid thermal annealing (RTA).

Keywords

CMOS memory circuits; SRAM chips; integrated circuit interconnections; integrated circuit technology; leakage currents; low-power electronics; phase shifting masks; photoresists; tungsten; 0.15 micron; CMOS ultra-low power SRAM cell; W damascene interconnection; buried channel pMOS; direct contact; leakage current; phase shift mask; photoresist reflow; single gate technology; CMOS process; CMOS technology; Displays; Fabrication; Leakage current; MOSFETs; Power generation; Random access memory; Rapid thermal annealing; Rapid thermal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904386

Filename

904386