Title :
Automatic generation of functional test pattern for the SCHOLAR system
Author :
Wong, Mike Wai-Tak ; Nichols, Ken G.
Author_Institution :
Dept. of Electron. Eng., Hong Kong Polytech., Kowloon, Hong Kong
Abstract :
An automatic functional test pattern generation method for the control path generated by the SCHOLAR system is presented in this paper. The method is based on the scan path design incorporated with the input partitioning technique. The main features of this method are: (i) a guaranteed 100% coverage of the single input and output stuck-at-faults; and (ii) a substantial reduction in hardware overhead. Another novelty is that the test pattern generation step is completely automatic without the use of a fault simulator or any commercial ATPG tools
Keywords :
automatic test equipment; circuit layout CAD; logic testing; 100% coverage; ATPG; SCHOLAR system; automatic test pattern generation; control path; fault coverage; features; functional test pattern generation; hardware reduction; input partitioning technique; scan path design; stuck-at-faults; Automata; Automatic test pattern generation; Automatic testing; Circuit faults; Clocks; Control systems; Electronic equipment testing; Equations; System testing; Test pattern generators;
Conference_Titel :
Circuits and Systems, 1991. Conference Proceedings, China., 1991 International Conference on
Conference_Location :
Shenzhen
DOI :
10.1109/CICCAS.1991.184443
