Author :
Chiarella, T. ; Rosmeulen, M. ; Tigelaar, H. ; Kerner, C. ; Nackaerts, A. ; Ramos, J. ; Lauwers, A. ; Veloso, A. ; Jurczak, M. ; Rothschild, A. ; Witters, L. ; Yu, H. ; Kitt, J.A. ; Verbeeck, R. ; de Potter, M. ; Debusschere, I. ; Absil, P. ; Biesemans, S
Abstract :
The integration of fully silicided gates on a high-k dielectric in a standard process flow offers a solid alternative to the conventional Poly/SiON devices. In this work, we provide an extensive analysis of the module yield extracted for such devices highlighting the need for specific additional alarm flags without which some integration problems might be overlooked. The impact at the circuit level is studied and supported by modeling work on simple ring-oscillators.
Keywords :
high-k dielectric thin films; integrated circuit modelling; integrated circuit yield; oscillators; FUSI specific yield monitoring; alarm flags; circuit level modeling; circuit performance; fully silicided gates integration; high-k dielectrics; module yield analysis; ring-oscillators; standard process flow; Circuit optimization; Circuit testing; Delay; Feedback circuits; High-K gate dielectrics; Microelectronics; Monitoring; Performance evaluation; Production; Tellurium; FUSI; VT splitting; Yield; delay; power; ring-oscillator;
