Title :
Test Circuit for Study of CMOS Process Variation by Measurement of Analog Characteristics
Author :
Gettings, Karen M G V ; Boning, Duane S.
Author_Institution :
MIT, Cambridge
Abstract :
We propose and demonstrate a test chip for extraction of spatial and layout dependent variations in both transistor and interconnect structures. A scan chain approach is combined with low-leakage and low-variation switches, providing access to detailed analog device characteristics in large arrays of test devices. Compared to digital test structures such as ring oscillators, the test circuit enables flexible extraction and analysis of variation in any device model parameters based on current-voltage measurements.
Keywords :
CMOS analogue integrated circuits; capacitance; integrated circuit interconnections; integrated circuit layout; integrated circuit measurement; integrated circuit modelling; integrated circuit testing; transistors; CMOS process variation; analog characteristics measurement; analog device characteristics; current-voltage measurements; device model parameters; interconnect structures; layout dependent variations; low-leakage switches; low-variation switches; scan chain approach; spatial dependent variations extraction; test chip; test circuit; test structures; transistor structures; CMOS process; Capacitance measurement; Circuit testing; Current measurement; Fingers; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit testing; Semiconductor device measurement; Switches; CBCM; Test Structures; low-leakage switches; scan chain;
Conference_Titel :
Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on
Conference_Location :
Tokyo
Print_ISBN :
1-4244-0781-8
Electronic_ISBN :
1-4244-0781-8
DOI :
10.1109/ICMTS.2007.374451
