DocumentCode
2886621
Title
A sizing methodology for a low-noise comparator
Author
Lai, Kuo-Hsin ; Huang, Shi-Yu ; Chiang, Pei-Chia
Author_Institution
Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan
Volume
1
fYear
2004
fDate
6-9 Dec. 2004
Firstpage
253
Abstract
We present a methodology to reduce the charge injection noise for an offset-free comparator, so as to achieve a higher resolution. Our method incorporates an algorithm that automatically searches for the optimal transistor sizes in the comparator. The values of this methodology are in two aspects. First, it takes away from designers the burden of sizing the transistors. Second, it is fully automatic and could ease the technology migration process. Experimental results show that the resolution can be improved by an order of magnitude through this methodology.
Keywords
charge injection; comparators (circuits); operational amplifiers; charge injection noise; low-noise comparator; offset-free comparator; optimal transistor size; sizing methodology; Analog-digital conversion; Capacitance; Capacitors; Circuit noise; Noise cancellation; Noise reduction; Pulse inverters; Signal resolution; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Print_ISBN
0-7803-8660-4
Type
conf
DOI
10.1109/APCCAS.2004.1412741
Filename
1412741
Link To Document