DocumentCode
2886643
Title
A rail-to-rail, constant gain CMOS op-amp
Author
Liang, Yung-Chih ; Sheu, Meng-Lieh ; Hsu, Wei Hung
Author_Institution
Dept. of Electr. Eng., Nat. Chi-Nan Univ., Nan-Tou Hsien, Taiwan
Volume
1
fYear
2004
fDate
6-9 Dec. 2004
Firstpage
257
Abstract
A rail-to-rail constant gain CMOS operational amplifier was designed by using complementary differential input stage and current compensation skills. The chip was implemented by a 0.35μm 1P4M CMOS standard logic process. The measurement results show that the chip can achieve 110dB gain, 13.6MHz bandwidth, and 1.275mW power consumption, when operating at 3V and 35pF load.
Keywords
CMOS logic circuits; differential amplifiers; operational amplifiers; 0.35 micron; 1.275 mW; 110 dB; 13.6 MHz; 1P4M CMOS standard logic process; 3 V; 35 pF; complementary differential input stage; current compensation skill; operational amplifier; rail-to-rail constant gain CMOS op-amp; CMOS logic circuits; CMOS process; Differential amplifiers; Gain measurement; Operational amplifiers; Power measurement; Rail to rail amplifiers; Rail to rail inputs; Rail to rail operation; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Print_ISBN
0-7803-8660-4
Type
conf
DOI
10.1109/APCCAS.2004.1412742
Filename
1412742
Link To Document