A 1 Mbit SRAM test structure to analyze local mismatch beyond 5 sigma variation

Author

Fischer, Thomas ; Otte, Christopher ; Schmitt-Landsiedel, Doris ; Amirante, Ettore ; Olbrich, Alexander ; Huber, Peter ; Ostermayr, Martin ; Nirschl, Thomas ; Einfeld, Jan

Author_Institution

Tech. Univ. of Munich, Munich

fYear

2007

fDate

19-22 March 2007

Firstpage

63

Lastpage

66

Abstract

We present an area efficient test structure that allows a measurement of the statistical distribution of SRAM cell currents beyond 5 sigma variation. The test structure was fabricated in a 90 nm and a 65 nm CMOS technology. The measured data show that the device variations are Gaussian-distributed for more than 1 million devices, covering more than 5 sigma of variation. Monte Carlo simulations are used to validate the measurements.

Keywords

CMOS memory circuits; Gaussian distribution; Monte Carlo methods; SRAM chips; circuit simulation; electric current; integrated circuit testing; CMOS technology; Gaussian-distribution; Monte Carlo simulations; SRAM cell currents; SRAM test structure; local mismatch analysis; size 65 nm; size 90 nm; statistical distribution measurement; storage capacity 1 Mbit; CMOS technology; Current measurement; Decoding; Electronic equipment testing; Gaussian distribution; Logic arrays; Logic testing; MOSFETs; Random access memory; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on

Conference_Location

Tokyo

Print_ISBN

1-4244-0781-8

Electronic_ISBN

1-4244-0781-8

Type

conf

DOI

10.1109/ICMTS.2007.374456

Filename

4252406