Impact of Sinter Process and Metal Coverage on Transistor Mismatching and Parameter Variations in Analog CMOS Technology

In this paper, we report detailed studies on the impacts of sinter process and metal coverage on CMOS transistor matching and parameter variability in an analog CMOS technology. Transistor matching and parameter variations with different metal slotting sizes processed at different sinter temperatures have also been studied. It has been found that both metal plating and sinter temperature play critical roles in transistor matching and parameter variation. Metal plating degrades VT and current matching (VT offset ~30 mV, DeltaI/I~18% at moderate inversion and DeltaI/I~3% at strong inversion) significantly at low sinter temperature. Metal slotting array of size 15umX15um with 5um separation over the transistor array has been demonstrated to be very effective in reducing the systematic mismatching. The transistor mismatching improves at higher sinter temperature. Calculated current variations agree well with experimental results.