Title :
Effect of polysilicon gate on the flatband voltage shift and mobility degradation for ALD-Al/sub 2/O/sub 3/ gate dielectric
Author :
Lee, J.H. ; Koh, K. ; Lee, N.I. ; Cho, M.H. ; Ki, Y.K. ; Jeon, J.S. ; Cho, K.H. ; Shin, H.S. ; Kim, M.H. ; Fujihara, K. ; Kang, H.K. ; Moon, J.T.
Author_Institution :
Samsung Electron. Co. Ltd., Kyunggi-Di, South Korea
Abstract :
Al/sub 2/O/sub 3/ (EOT=22.7 /spl Aring/) gate dielectric layer formed by Atomic Layer Deposition (ALD) process have been characterized for sub-100 nm CMOS devices. The gate leakage current was 3 orders of magnitude lower than that of SiO/sub 2/ and the hysteresis of C-V curve was not observed. However, the negative fixed charge induced the flat band voltage (Vfb) shift and degraded the channel mobility of MOS transistor. The Vfb shift was reduced and channel mobility was improved by applying P+ gate by BF/sub 2/ implantation. It is suggested that the phosphorous diffused from gate polysilicon has a role of network modifier in Al/sub 2/O/sub 3/ film and formation of the Al-O- dangling bond which may be ascribed to negative fixed charge.
Keywords :
MOSFET; alumina; carrier mobility; dangling bonds; dielectric thin films; diffusion; ion implantation; leakage currents; vacuum deposited coatings; 100 nm; Al/sub 2/O/sub 3/ gate dielectric; BF/sub 2/ implantation; CMOS device; MOS transistor; Si-Al/sub 2/O/sub 3/; atomic layer deposition; capacitance-voltage characteristics; channel mobility; dangling bond; flatband voltage; leakage current; negative fixed charge; phosphorus diffusion; polysilicon gate; Atomic layer deposition; CMOS process; Capacitance-voltage characteristics; Channel bank filters; Degradation; Dielectric devices; Hysteresis; Leakage current; MOSFETs; Voltage;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904402
