Title :
Test Structure for Process and Product Evaluation
Author :
Rigaud, F. ; Portal, J.M. ; Aziza, H. ; Nee, D. ; Vast, J. ; Auricchio, C. ; Borot, B.
Author_Institution :
UMR CNRS, Marseille
Abstract :
The objective of this paper is to present a test structure introduced in the scribe lines designed to detect process drift and to characterize product performances, i.e. delay and VDDmin. A brief overview of the structure, designed in a ST-Microelectronics 130nm technology, is given. The main advantages of the structure are to be introduced in the scribe line and to have a complex architecture close to the product back-end configurations. A specific test flow is applied to the structure in order to extract relevant data (frequency, delay and bias). The monitoring efficiency of the structure is validated with measurement correlation performed on the structure data, parametric test data and full test chip data.
Keywords :
CMOS integrated circuits; integrated circuit testing; process monitoring; system-on-chip; CMOS ST-Microelectronics technology; full test chip data; measurement correlation; monitoring efficiency; parametric test data; process drift detection; product back-end configurations; scribe lines; size 130 nm; system-on-chips technology; test structure; Automatic testing; CMOS technology; Condition monitoring; Data mining; Delay; Electric variables measurement; Microelectronics; Performance evaluation; Production; Semiconductor device measurement;
Conference_Titel :
Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on
Conference_Location :
Tokyo
Print_ISBN :
1-4244-0781-8
Electronic_ISBN :
1-4244-0781-8
DOI :
10.1109/ICMTS.2007.374471