Thermal characteristics of multi-die, three-dimensional integrated circuits with unequally sized die

Three-dimensional integrated circuits (3D ICs) technology involves significant thermal management challenges due to the overlap of heat dissipation from several die. One particular problem is related to the thermal management of a multi-die stack with unequally-sized die. This is an important problem since several 3D IC process integration technologies requires unequally sized die. This paper investigates several thermal management and design issues in such a scenario. A resistance-network based model for a multi-die stack with unequally sized die is developed and validated using full finite-element simulations. In case all die dissipate the same power density, the model shows that as expected, it is thermally optimal to place the largest die nearest to the heat sink. On the other hand, if all die dissipate the same total power, the thermally optimal sequence calls for placing the two largest die at the two ends of the stack, in order to minimize the stack-to-package and stack-to-heatsink thermal resistances. In addition to these validation cases, the model enables prediction of temperature profiles for a general case with non-uniform die sizes, powers and power distributions, where the optimal sequence is not obvious. For example, in a somewhat surprising result, it is shown that the impact of choosing a thermally optimized stack sequence is somewhat diminished in the presence of hotspots on the die. It is shown that given the total silicon area, it is thermally optimal to partition the silicon area into equal-sized die, although this may be in conflict with the most economical option for manufacturing 3D ICs.