DocumentCode :
2887065
Title :
A 256K CMOS SRAM with internal refresh
Author :
Hanamura, S. ; Minato, O. ; Masuhara, T. ; Sakai, Yoshiki ; Yamanaka, T. ; Moriwaki, Nobihiro ; Kojima, Fumihide
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Volume :
XXX
fYear :
1987
fDate :
0-0 Feb. 1987
Firstpage :
250
Lastpage :
251
Abstract :
A four-transistor switched-capacitor load SRAM employing 0.8μm CMOS technology with a cell size of 39.2μm2will be reported. The approach makes it possible to access without time-loss for internal refresh. Access time is 43ns and standby power is 3.3μW.
Keywords :
Capacitors; Circuits; Conductivity; Flip-flops; Power engineering and energy; Random access memory; Read-write memory; Signal generators; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1987.1157079
Filename :
1157079
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2887065
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