Modelling and design of single-edge oversampled PWM current regulators using z-domain methods

This paper takes a fundamental look at the mechanisms underlying the stability of single-edge pulse-width modulated current regulator loops. The analysis applies to continuous-time or highly oversampled digital current regulators. It is shown that pulse-width modulation is essentially a sampling process. Associated with this sampling process is a small-signal z-domain model of the pulse-width modulator which is used to accurately predict the stability of the control loop. A method for designing the current regulator directly in this z-domain is presented. A technique for delay-less ripple feedback compensation is presented. Finally it is shown how computational and other delays in the loop can be compensated for during the design process.