Title :
Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs
Author :
Sungjun Im ; Banerjee, K.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
This work presents a full chip thermal analysis of 2-D high performance ICs based on technological, structural, and material data from ITRS ´99. It is shown that interconnect Joule heating in advanced technology nodes can strongly impact the magnitude of the maximum temperature within 2-D chips despite negligible change in the chip power density, as per the ITRS. This result has been shown to have significant implications for interconnect reliability and performance not foreseeable by the ITRS. Furthermore, detailed thermal analysis of vertically integrated (3-D) ICs has been carried out using analytical modeling and numerical simulations. Additionally, comparison between the thermal design of two alternative 3-D technologies has been presented for the first time using ITRS data.
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; thermal analysis; 2D high performance ICs; 3D ICs; analytical modeling; chip power density; full chip thermal analysis; interconnect Joule heating; interconnect reliability; maximum temperature magnitude; thermal design; vertically integrated ICs; Boundary conditions; Conducting materials; Delay; Equations; Heating; Integrated circuit interconnections; Performance analysis; Temperature; Thermal conductivity; Thermal management;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904421
