DocumentCode :
2887144
Title :
On-wafer RF Figure-of-Merit Circuit Block Design for Technology Development, Process Control and PDK Validation
Author :
Minehane, S. ; Cheng, J. ; Nakatani, Takeshi ; Moriyama, Shinichi ; Aghdaie, B. ; Sengupta, Mainak ; Saxena, Shanky ; Winters, S. ; Karbasi, H. ; Quarantelli, M. ; Tonello, S. ; Redford, M.
Author_Institution :
PDF Solutions Inc., San Diego
fYear :
2007
fDate :
19-22 March 2007
Firstpage :
183
Lastpage :
186
Abstract :
The inclusion of circuit-level blocks, such as ring oscillators, operational amplifiers and A/D or D/A converters, in technology characterization test chips is now a well-established practice. Such figure-of-merit (FoM) circuit blocks provide a means of judging technology performance and variability on-wafer during the technology development phase. In addition, FoM blocks are used to validate the ability of a PDK in capturing process behavior. This paper describes an extension of this concept to the RF domain, for a high-performance 0.18mum SiGe:C-BiCMOS technology. The design of six different RF-FoM blocks, typically found in a transceiver, is presented. Test structure design considerations, including layout, pad-frame choice and probe-card design, are described. Finally, measured statistical results are presented. These designs enabled PDK verification and high-volume yield product samples.
Keywords :
BiCMOS integrated circuits; Ge-Si alloys; carbon; integrated circuit design; integrated circuit testing; process control; radiofrequency integrated circuits; BiCMOS technology; PDK validation; SiGe:C; circuit-level blocks; on-wafer RF figure-of-merit circuit block design; pad-frame choice; probe-card design; process control; size 0.18 mum; technology development; test structure design considerations; Circuit testing; Design optimization; Industrial control; Logic testing; Low-noise amplifiers; Microelectronics; Process control; Radio frequency; Radiofrequency amplifiers; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on
Conference_Location :
Tokyo
Print_ISBN :
1-4244-0781-8
Electronic_ISBN :
1-4244-0781-8
Type :
conf
DOI :
10.1109/ICMTS.2007.374479
Filename :
4252429
Link To Document :
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