Title :
A VLSI chip set for a massively parallel architecture
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
Abstract :
This paper will described two chips fabricated in 2μms CMOS. One chip contains 32 processors, and performs 320 million 4bit operations/s. The other chip a communications router, is capable of a throughput of 160Mbytes/s.
Keywords :
Circuit testing; Delay; Fabrication; Parallel architectures; Protocols; Registers; Switching circuits; Throughput; Very large scale integration; Wires;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157087
