DocumentCode
2887275
Title
A novel surface-oxidized barrier-SiN cell technology to improve endurance and read-disturb characteristics for gigabit NAND flash memories
Author
Goda, A. ; Moriyama, W. ; Hazama, H. ; Iizuka, H. ; Shimizu, K. ; Aritome, S. ; Shirota, R.
Author_Institution
Adv. Memory Device Group, Toshiba Corp., Yokohama, Japan
fYear
2000
fDate
10-13 Dec. 2000
Firstpage
771
Lastpage
774
Abstract
This paper describes a novel surface-oxidized barrier-SiN cell technology to effect a tenfold improvement in endurance and read disturb characteristics. In conventional memory cells, degradation of tunnel oxides due to barrier-SiN films for Self-Aligned Contact (SAC) limits the scaling of memory cells. The proposed technology overcomes this problem by an additional oxidation process subsequent to barrier-SiN deposition to reduce hydrogen in both SiN film and tunnel oxide. 0.18 /spl mu/m-rule NAND cells fabricated by the proposed technology demonstrate a tenfold improvement in allowable program/erase cycles and read disturb lifetime without any deterioration of other cell properties.
Keywords
NAND circuits; cellular arrays; flash memories; integrated circuit reliability; oxidation; 0.18 micron; NAND cells; SiN; allowable program/erase cycles; cell properties; disturb lifetime; endurance; gigabit NAND flash memories; oxidation process; read-disturb characteristics; surface-oxidized barrier-SiN cell technology; Etching; Flash memory; Hydrogen; MOS capacitors; Occupational stress; Oxidation; Pulp manufacturing; Silicon compounds; Thermal degradation; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-6438-4
Type
conf
DOI
10.1109/IEDM.2000.904431
Filename
904431
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