Title :
64 Kbit CMVP FeRAM macro with reliable retention/imprint characteristics
Author :
Kobayashi, S. ; Amanuma, K. ; Mori, H. ; Kasai, N. ; Maejima, Y. ; Seike, A. ; Tanabe, N. ; Tatsumi, T. ; Yamada, J. ; Miwa, T. ; Koike, H. ; Hada, H. ; Toyoshima, H.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
Packaged CMVP FeRAM chip reliability is evaluated for the first time. A 64 Kbit CMVP FeRAM macro is integrated with 0.35 /spl mu/m 3-level metallization CMOS logic devices. The ferroelectric properties of the PZT capacitor formed below 430/spl deg/C are not degraded even after plasma-SiON passivation. This is due to hydrogen barrier effect of TiN, and the high process damage immunity of the MOCVD PZT film. No failed bits are observed after a 240-hour retention/imprint period at temperatures between 25/spl deg/C and 150/spl deg/C with write/read voltages between 2.7 V and 5.5 V.
Keywords :
MOCVD coatings; ferroelectric capacitors; ferroelectric storage; integrated circuit metallisation; integrated circuit reliability; lead compounds; passivation; random-access storage; 0.35 micron; 2.7 to 5.5 V; 25 to 150 C; 430 C; 64 Kbit; CMOS logic device; CMVP FeRAM macro; PZT; PZT MOCVD film; PbZrO3TiO3; SiON; SiON plasma passivation; TiN; TiN hydrogen barrier; ferroelectric capacitor; imprint characteristics; memory cell; multilevel metallization; packaged chip reliability; retention characteristics; Capacitors; Ferroelectric films; Ferroelectric materials; Logic devices; Metallization; Nonvolatile memory; Packaging; Plasma properties; Plasma temperature; Random access memory;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904434
