Title :
Logical effort of carry propagate adders
Author :
Harris, Don ; Sutherland, Ivan
Author_Institution :
Harvey Mudd Coll., Claremont, CA, USA
Abstract :
A wide assortment of carry propagate adders offer varying area-delay tradeoffs. Wiring and choice of circuit family also affect the size and performance. This paper uses the method of logical effort to characterize the effects of architecture, circuit family, and wire capacitance on adder delay. Domino logic offers about a 30% speedup on most valency-2 adders. Although Kogge-Stone adders are fastest in the absence of wire, other architectures such as variants on the Sklansky adder offer regular layouts and better delay in the presence of wiring capacitance.
Keywords :
adders; carry logic; delays; logic design; network synthesis; Kogge-Stone adders; Sklansky adder; carry propagate adders; circuit family; delay tradeoffs; domino logic; logical effort; wire capacitance; Added delay; Adders; CMOS logic circuits; Capacitance; Computer architecture; Costs; Delay effects; Inverters; Wire; Wiring;
Conference_Titel :
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on
Print_ISBN :
0-7803-8104-1
DOI :
10.1109/ACSSC.2003.1292037
