A Novel RF-WAT Test Structure for Advanced Process Monitoring in SOC Applications

This paper presents a novel radio frequency (RF) structure for wafer acceptance test (WAT) to monitor RF device in the scribe line area with 60 mum or smaller in width. WAT including RF items for statistical analysis, yield enhancement and function verification is crucial for the success of system on chip (SoC). Conventional south-north GSG (C-GSG) structure, scribe line GSG (S-GSG) structure, which means a 2-port GSG in a row, GSGSG, and GSSG structure are used together with the proposed RF-WAT structure for silicon verification. Excellent mapping results of extensive application on RF-CV in 65 nm ultra-thin oxide CMOS devices at 12-inch wafer are also demonstrated.