DocumentCode
2887457
Title
A processor for graph search algorithms
Author
Glinski, S. ; Lalumia, T. ; Cassiday, D. ; Koh, T. ; Gerveshi, C. ; Wilson, G. ; Kumar, Jayant
Author_Institution
AT&T Bell Lab Speech Processing Department, Murray Hill, NY, USA
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
162
Lastpage
163
Abstract
This report will describe a programmable signal processor with a pipelined arithemetic unit capable of 40 MIPs operation in graph search kernel operations. Thus a fivefold improvement in speech and image processing algorithms can be obtained over conventional architectures The chip was fabricated in a 1.5μm CMOS technology, occupies 43.4mm2and operates at 20MHz.
Keywords
Algorithm design and analysis; Counting circuits; Decoding; GSM; Gold; Kernel; Signal analysis; Signal processing algorithms; Speech processing; Speech recognition;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157098
Filename
1157098
Link To Document