Systolic multiple-valued DTW processor

A new concept called `recursive systolic flow´ is proposed in this paper. It is adaptable to the formal algebraic design for complex systolic algorithm. A new systolic multiple-valued DTW (MV-DTW) processor is also presented which can achieve real-time isolated word recognition for large dictionaries. The MV-VLSI design proposed differs from previous systolic DTW design in that: ⟨1⟩ all data are represented in signed multiple-valued digits; ⟨2⟩ the algorithms are pipelined at bit level; ⟨3⟩ the processing elements are designed with MVPLAs; ⟨4⟩ data are passed between processing elements in a most significant bit first, serial fashion. The MV-DTW design has a high degree of concurrency and attains high data throughput. It is both flexible and modular