Undoped-emitter InP/InGaAs HBTs for high-speed and low-power applications

Author

Ida, M. ; Kurishima, K. ; Nakajima, H. ; Watanabe, N. ; Yamahata, S.

Author_Institution

NTT Photonics Labs., Kanagawa, Japan

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

854

Lastpage

856

Abstract

Scaling down the lateral emitter dimension is an effective way to reduce the power dissipation of HBT ICs. Various authors have demonstrated submicrometer HBTs operating at >100 GHz with submilliampere current. On the other hand, there have been few reports on vertical layer structures optimized for low-current operation. At low current, the dominant delay time of HBTs is the emitter charging time. Thus, it is essential to reduce the emitter junction capacitance by increasing the thickness of the emitter depletion layer. In this paper, we propose an undoped-emitter structure for InP-based HBTs and investigate its impact on low-power applications.

Keywords

III-V semiconductors; bipolar integrated circuits; capacitance; circuit simulation; delays; gallium arsenide; indium compounds; integrated circuit modelling; low-power electronics; HBT ICs; InP-InGaAs; delay time; emitter charging time; emitter depletion layer; emitter junction capacitance; lateral emitter dimension; low-current operation; low-power applications; power dissipation; submilliampere current; vertical layer structures; Capacitance; Delay effects; Doping; Electron devices; Heterojunction bipolar transistors; Indium gallium arsenide; Indium phosphide; Photonics; Power dissipation; Thermionic emission;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904451

Filename

904451