DocumentCode
2887643
Title
A piepline sorting chip
Author
Tsuda, Naoaki ; Satoh, T. ; Kawada, T.
Author_Institution
NTT Electrical Communication Laboratories, Tokyo, Japan
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
270
Lastpage
271
Abstract
A 3μm, double metal CMOS pipeline sorter ship that selects 80 16-byte records at a 3Mbytes/s throughput rate will be disclosed. The 37×21mm chip uses hierarchical redundancy and laser repair to increase yield by 10× with an eara of only 1.9×.
Keywords
Artificial intelligence; Built-in self-test; CMOS technology; Circuit testing; Corporate acquisitions; Distributed computing; Large scale integration; Merging; Sorting; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157107
Filename
1157107
Link To Document