Title :
A 35ns 1Mb CMOS SRAM
Author :
Komatsu, T. ; Okazaki, N. ; Nishihara, T. ; Kayama, S. ; Hoshi, N. ; Aaoyama, J. ; Shimada, Toshikazu
Author_Institution :
Sony Semiconductor Group, Kanagawa, Japan
Abstract :
A 128×8b CMOS SRAM with TTL input/output levels will be presented. The SRAM has been fabricated in a 1.0μm double-poly silicon double-metal CMOS technology Chip size is 8×13.65mm. Typical standby current is 5μA with 100mW dissipatlon at 10MHz. Noise immunity has been achieved from a dual threshold level data transfer.
Keywords :
Artificial intelligence; CMOS process; Circuits; Electronics packaging; MOS devices; Power dissipation; Random access memory; Read-write memory; Yagi-Uda antennas;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157110
