Bounding the design space in hardware allocation

The authors describe the structure of the FIDIAS system, a high level synthesis tool. They also describe in more detail HARAL, the FIDIAS module accomplishing the hardware allocation subtask. The three main features of HARAL are shown, while the data path model and the algorithm used for exploring the resulting design space are given, as well as the criteria employed for design cost estimation. The techniques used to bound the accessible design space in order to reduce the search times are also shown