Title :
Stencil mask ion implantation technology for high performance MOSFETs
Author :
Shibata, T. ; Suguro, K. ; Sugihara, K. ; Mizuno, H. ; Yagishita, A. ; Saito, T. ; Okumura, K. ; Nishihashi, T. ; Gotou, T. ; Tsunoda, M. ; Saji, S.
Author_Institution :
Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
Abstract :
Stencil mask implantation technology was applied to Damascene metal gate MOSFET fabrication process. p-MOSFET can be successfully fabricated by using phosphorous channel implants with improved stencil masks. The threshold voltage values can be controlled by implanted dose as well as conventional implants. The present technology is effective in reducing raw process time, equipment cost and clean room space.
Keywords :
MOSFET; clean rooms; ion implantation; masks; Damascene metal gate MOSFET; MOSFET fabrication process; Si:P; channel implants; clean room space; equipment cost; implanted dose; raw process time; stencil mask ion implantation technology; threshold voltage values; Biomembranes; Dielectric substrates; Doping; Electrodes; Implants; Ion implantation; MOSFET circuits; Nitrogen; Resists; Semiconductor films;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904456
