Author :
Takano, S. ; Makino, H. ; Tanino, N. ; Noda, M. ; Nishitani, K. ; Kayano, S.
Author_Institution :
Mitsubishi LSI Research and Development Laboratory, Hyogo, Japan
Abstract :
A GaAs SRAM utilizing a self aligned FET and double-level metal technology will be disclosed. Address predecoders and controlled gain stage loading give an access time of 15ns. A 5.8×4.7mm chip dissipates´ 1W with a power supply of 1V.
Keywords :
Computer industry; Electron devices; FETs; Gallium arsenide; International trade; Metal-insulator structures; Power dissipation; Pulse amplifiers; Random access memory; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157112
