Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS

Determinant factors of the minimum operating voltage (V_DDmin) of CMOS logic gates are investigated by measurements of logic-gate chains in 65nm CMOS. V_DDmin consists of a systematic component (V_DDmin(SYS)) and a random variation component (V_DDmin(RAND)). V_DDmin(SYS) is minimized, when the logic threshold voltage of logic gates equals to half supply voltage (V_DD). The tuning of the logic threshold voltage of each logic gate is achieved by the sizing of the gate width of nMOS/pMOS. V_DDmin(RAND) is minimized by reducing the random threshold variation achieved by increasing the gate width or the forward body biasing. In addition, the temperature dependence of V_DDmin is measured for the first time. The temperature for the worst corner analysis for V_DDmin should be changed depending on the number of gate counts of logic circuits.