Title :
A 5ns access time 64Kb ECL RAM
Author :
Awaya, T. ; Toyoda, K. ; Nomura, O. ; Nakaya, Y. ; Tanaka, K. ; Sugawara, H.
Author_Institution :
Fujitsu Bipolar Memory Design, Kawasaki, Japan
Abstract :
An 8K×8 bipolar ECL RAM with segmented bit lines and Darlington drive circuits will be described. RAM uses the sharing signal line technique. Wafer process yield is obtained by use of a memory cell with deep P-well base diffusion and two row redundancy.
Keywords :
Capacitance; Cutoff frequency; Driver circuits;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157113
