Author :
Suzuki, A. ; Yamaguchi, S. ; Ito, H. ; Suzuki, N. ; Yabu, T.
Author_Institution :
Fujitsu MOS Memory, Process Divisions, Kawasaki, Japan
Abstract :
A CMOS memory for cache systems which includes 49K bits SRAM and about 3500 transistors for logic will be presented. The memory achieves access times of 19ns from address to hit and 9.5ns from tag to hit, using address transition detection.
Keywords :
Cache memory; Decoding; Electronics packaging; Logic; RNA;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157127
