• DocumentCode
    2888011
  • Title

    A 19ns memory

  • Author

    Suzuki, A. ; Yamaguchi, S. ; Ito, H. ; Suzuki, N. ; Yabu, T.

  • Author_Institution
    Fujitsu MOS Memory, Process Divisions, Kawasaki, Japan
  • Volume
    XXX
  • fYear
    1987
  • fDate
    0-0 Feb. 1987
  • Firstpage
    134
  • Lastpage
    135
  • Abstract
    A CMOS memory for cache systems which includes 49K bits SRAM and about 3500 transistors for logic will be presented. The memory achieves access times of 19ns from address to hit and 9.5ns from tag to hit, using address transition detection.
  • Keywords
    Cache memory; Decoding; Electronics packaging; Logic; RNA;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1987.1157127
  • Filename
    1157127
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2888011