Title :
A GaAs 1K SRAM with 2ns cycle time
Author :
Gabillard, B. ; Rocher, C. ; Ducourant, T. ; Prost, M.
Author_Institution :
Electronics and Physics Applications Laboratories, Limeil-Brevannes, France
Abstract :
An ECL compatible SRAM that attains rise and fall times of 200ps with a power consumtpion of 210mW will be described. Word line clamping and data bus delay reduction allow control of the access time in spite of threshold voltage varation of 90mV.
Keywords :
Cache memory; Circuit simulation; Delay effects; Differential amplifiers; Driver circuits; Gallium arsenide; Paper technology; Random access memory; Switches; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157128
