DocumentCode :
2888065
Title :
A 50ns DSP with parallel processing architecture
Author :
Kaneko, Kunihiko ; Nakagawa, T. ; Kiuchi, A. ; Hagiwara, Y. ; Ueda, Hiroshi ; Matsushima, Hirokazu ; Akazawa, Toshinobu ; Satoh, T. ; Jun Ishida
Author_Institution :
Hitachi Central Research Laboratory, Tokyo, Japan
Volume :
XXX
fYear :
1987
fDate :
0-0 Feb. 1987
Firstpage :
158
Lastpage :
159
Abstract :
This report will cover a programmable DSP that avoids I/O bottlenecks through a two-level hierarchy of instructions. The IC contains 430K transistors on a 149mm2die.
Keywords :
Automatic control; Circuits; Data processing; Digital signal processing; Filtering; Parallel processing; Pixel; Random access memory; Read-write memory; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1987.1157130
Filename :
1157130
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2888065
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