Title :
A 64K GaAs gate array
Author :
Terada, T. ; Ikawa, Y. ; Kameyama, A. ; Kawakyu, K. ; Sasaki, T. ; Kitaura, Y. ; Ishida, K. ; Nishihori, K. ; Toyoda, N.
Author_Institution :
Toshiba VLSI Research Center, Kawasaki, Japan
Abstract :
This paper will report on a gate array that employs Schottky diode capacitor-coupled logic to attain a noise margin of 400mV. At a power dissipation of 1mW%gate, the propagation delay was 284ps.
Keywords :
Circuit noise; Clocks; Data conversion; Delay effects; FETs; Gallium arsenide; Power dissipation; Shift registers; Solid state circuits; Space technology;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157131
