• DocumentCode
    2888126
  • Title

    A 300Mb/s clock recovery and data retiming system

  • Author

    Andrews, G. ; Farley, D. ; Kravitz, S. ; Schelling, A. ; Davis, P. ; McAfee, L.

  • Author_Institution
    AT&T Bell Laboratories, Allentown, PA
  • Volume
    XXX
  • fYear
    1987
  • fDate
    0-0 Feb. 1987
  • Firstpage
    188
  • Lastpage
    189
  • Abstract
    A single bipolar chip housed with a Surface Acoustic Wave filter in a multi-cavity ceramic DIP to provide clock recovery and data retiming up to 300Mb/s will be discussed. Device accepts a jittered data input and provides a low jitter clock ( < 3^{\\circ} rms)and retimed data with 10% eye width closure on ECL balanced outputs.
  • Keywords
    Capacitance; Clocks; Delay; Frequency; Pulse amplifiers; RLC circuits; SAW filters; Surface acoustic waves; Temperature; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1987.1157134
  • Filename
    1157134
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2888126