DocumentCode
2888228
Title
Automated data path synthesis to avoid global interconnects
Author
Raj, V.K. ; Patwardhan, C.S.
Author_Institution
Dept. of Comput. Sci. Eng., Texas Univ., Arlington, TX, USA
fYear
1991
fDate
4-8 Jan 1991
Firstpage
11
Lastpage
16
Abstract
Incorporates into a behavioral synthesis system an algorithm to minimize global interconnects in the data path. In order to accomplish this, the authors define a model of the data path to almost completely avoid global interconnects. In this approach, they pay the penalty of extra registers and extra microinstructions to avoid global interconnects. The proposed model of the data path results in large area savings in behavioral synthesis
Keywords
VLSI; circuit CAD; logic CAD; shift registers; area savings; behavioral synthesis system; data path; global interconnects; microinstructions; registers; Algorithm design and analysis; Computer science; Data engineering; High level synthesis; Multiplexing; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location
New Delhi
Print_ISBN
0-8186-2125-7
Type
conf
DOI
10.1109/ISVD.1991.185085
Filename
185085
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