Fault modeling and testable design of 2-level complex ECL gates

Author

Menon, Sankaran M. ; Malaiya, Yashwant K. ; Jayasumana, Anura P.

Author_Institution

Colorado State Univ., Fort Collins, CO, USA

fYear

1991

fDate

4-8 Jan 1991

Firstpage

23

Lastpage

28

Abstract

Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behaviour of 2-level complex ECL gates is examined in the presence of physical faults. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. A testable design approach is presented for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementation for ECL devices

Keywords

emitter-coupled logic; fault location; logic design; logic gates; augmented stuck-at fault model; complementary outputs; complex ECL gates; error conditions; physical faults; power consumption; testable design; two-level circuits; Circuit faults; Circuit testing; Computer science; Coupling circuits; Integrated circuit technology; Logic circuits; Logic design; Logic devices; Logic testing; Monitoring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on

Conference_Location

New Delhi

Print_ISBN

0-8186-2125-7

Type

conf

DOI

10.1109/ISVD.1991.185087

Filename

185087