Title :
A 90ns 4Mb DRAM in a 300 mil DIP
Author :
Mashiko, K. ; Nagatomo, Makoto ; Arimoto, Keisuke ; Matsuda, Yuuki ; Furutani, K. ; Matsukawa, T. ; Yoshihara, Tatsuhiko ; Nakano, T.
Author_Institution :
Mitsubishi Electric Corporation, Hyogo, Japan
Abstract :
A 4Mb DRAM employing a folded-bitline adaptive sidewall - isolated capacitance cell with 2μm deep trenches, a 72.3mm2chip size and 90ns access time will be described. Also incorporated are full bonding options for 4Mb×1 or 1Mb×4 organizations and for static column or page-mode operation.
Keywords :
Capacitors; Circuit testing; Clocks; Electronics packaging; Large scale integration; Preamplifiers; Random access memory; Read-write memory; Research and development; Semiconductor device packaging;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157143
