• DocumentCode
    2888344
  • Title

    A 130K-gate mainframe chip set

  • Author

    Ikeda, Ken-ichi ; Yamagiwa, A. ; Ikuzaki ; Fujita, Masayuki ; Masaki, A. ; Asano, Masahiro

  • Author_Institution
    Hitachi Kanagawa Works, Device Development Center, Central Research Laboratory, Kanagawa, Japan
  • Volume
    XXX
  • fYear
    1987
  • fDate
    0-0 Feb. 1987
  • Firstpage
    86
  • Lastpage
    87
  • Abstract
    This presentation will cover a mainframe chip set using three VLSIs containing 542K transistors, employing a rapid turn-around standard cell design methodology. Employing 1.3μm buld processing and controlled by an 8-phase clocking system, the chip operates with a cycle time of less than 60ns and an average propagation delay of less than 0.9ns.
  • Keywords
    Arithmetic; CMOS process; Cache storage; Decoding; Delay effects; Gold; Logic; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1987.1157144
  • Filename
    1157144
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2888344