Title :
A 130K-gate mainframe chip set
Author :
Ikeda, Ken-ichi ; Yamagiwa, A. ; Ikuzaki ; Fujita, Masayuki ; Masaki, A. ; Asano, Masahiro
Author_Institution :
Hitachi Kanagawa Works, Device Development Center, Central Research Laboratory, Kanagawa, Japan
Abstract :
This presentation will cover a mainframe chip set using three VLSIs containing 542K transistors, employing a rapid turn-around standard cell design methodology. Employing 1.3μm buld processing and controlled by an 8-phase clocking system, the chip operates with a cycle time of less than 60ns and an average propagation delay of less than 0.9ns.
Keywords :
Arithmetic; CMOS process; Cache storage; Decoding; Delay effects; Gold; Logic; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157144
